DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 686

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–14
Stratix IV Device Handbook Volume 2: Transceivers
FPGA Fabric PLLs-Transceiver PLLs Cascading Rules
1
You can only cascade the left PLLs (PLL_L1, PLL_L2, PLL_L3, and PLL_L4) to the
transceiver blocks located on the left side of the device. Similarly, you can only
cascade the right PLLs (PLL_R1, PLL_R2, PLL_R3, and PLL_R4) to the transceiver blocks
located on the right side of the device.
The PLL cascade networks are single clock lines segmented by bidirectional tri-state
buffers located along the clock line. Segmentation of the PLL cascade network allows
two left and right PLLs to drive the cascade clock line simultaneously and provides
the input reference clock to the CMU PLLs and receiver CDRs in different transceiver
blocks. When cascading two or more FPGA fabric PLLs to the CMU PLLs and receiver
CDRs, there must be no crossover in the cascaded clock paths on the PLL cascade
network
For better noise rejection, ensure the bandwidth setting of the FPGA fabric PLL (the
upstream PLL) is lower than the transceiver PLL (the downstream PLL).
Example 2: Design Target—EP4SGX530NF45 Device
If your design is targeted for a EP4SGX530NF45 device, it requires providing input
reference clocks to the following CMU PLLs and receiver CDRs from two right PLLs
in the FPGA fabric:
■
■
Case 1: use PLL_R4 to provide the input reference clock to the receiver CDRs in
channel 2 and channel 3 (shown in GREEN) and use PLL_R1 to provide the input
reference clock to the CMU0 PLL (shown in BLUE) in transceiver block GXBR1.
CMU0 PLL in Transceiver Block GXBR1
Receiver CDRs in channel 2 and channel 3 in Transceiver Block GXBR1
(Figure
2–9).
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
February 2011 Altera Corporation