DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 911
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 911 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–34. Read Transaction in Data Rate Division in Transmitter Mode
Note to
(1) For this example, the existing local divider settings of the transmitter channel are Divide by 2. Therefore, the value read out at
February 2011 Altera Corporation
rate_switch_out[1:0] is 2'b01.
logical_channel_address (1)
Figure
reconfig_mode_sel[2:0]
rate_switch_out[1:0]
5–34:
f
1
reconfig_clk
data_valid
For this example, the value set in the What is the number of channels controlled by
the reconfig controller? option of the ALTGX_RECONFIG MegaWizard Plug-In
Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. Also, you
must read the existing local divider settings of the transmitter channel whose logical
channel address is 2'b01.
division in transmitter mode.
busy
Do not perform a read transaction in date rate division in transmitter mode if
rate_switch_out[1:0] is not selected in the ALTGX_RECONFIG MegaWizard
Plug-In Manager.
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
read
2'bXX
3'bXXX
2'bXX
Figure 5–34
Invalid output
shows a read transaction waveform in data rate
3'b011
2'b01
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
2'bXX
2'b01
5–65
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