DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 553

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
f
Clocks for the Transmitter Serializer
When you configure the CMU channel as a transceiver channel, the clocks for the
transmitter side is provided by one of these sources:
■
■
■
Input Reference Clocks for the Receiver CDR
When you configure a CMU Channel as a transceiver channel, there are multiple
sources of input reference clocks for the receiver CDR:
■
■
For more information, refer to the “Input Reference Clocking” section of the
Transceiver Clocking in Stratix IV Devices
Clocks for the Receiver Deserializer
The CDR provides high-speed serial and low-speed parallel clocks to the receiver
deserializer from the recovered data.
Other CMU Channel Features
The CMU channels provide the following features:
■
■
■
For more information about analog controls and OCT, refer to
Buffer” on page 1–34
For information about loopback, refer to
The other CMU channel in the same transceiver block that is configured as a clock
multiplication unit
From CMU channel0 on the other transceiver block on the same side of the device
through the ×N clock line (the ×N_Top or ×N_Bottom clock line). If you configure a
CMU channel in Basic (PMA Direct) ×N mode, you can use this clocking option
From one of the ATX PLL blocks on the same side of the device through the ×N
clock line (the ×N_Top or ×N_Bottom clock line)
From adjacent REFCLKs within the same transceiver block, if the adjacent CMU
Channel is not used as a transceiver channel
From the REFCLK of adjacent transceiver blocks on the same side of the device, if
the corresponding CMU channels are not used as transceiver channels. For
REFCLK connections to the CMU channel from the global clock lines and PLL
cascade network, refer to
Analog control options—Differential output voltage ( V
equalization, and DC gain settings present in the regular channels are also
available in the CMU channels.
OCT—CMU channels can have an OCT feature. The allowed termination values
are the same as regular channels (85, 100, 120, and 150 Ω).
Loopback—The available loopback options are serial, reverse serial (pre-CDR),
and reverse serial (CDR) loopback.
and
“Receiver Input Buffer” on page
Table 1–6 on page
chapter.
“Loopback Modes” on page
1–18.
Stratix IV Device Handbook Volume 2: Transceivers
OD
1–40.
), pre-emphasis,
“Transmitter Output
1–190.
1–109