DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 203
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 203 of 1154
- Download datasheet (32Mb)
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
LVDS Input OCT (R
Summary of OCT Assignments
f
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 Ω , as shown in
in row I/O banks when both the V
do not support OCT R
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support R
Figure 6–22. Differential Input OCT
For more information about differential on-chip termination, refer to the
Differential I/O Interfaces and DPA in Stratix IV Devices
Table 6–9
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Input Termination
Output Termination
Note to
(1) You can enable differential OCT R
Assignment Name
Table
lists the OCT assignments for the Quartus II software version 9.1 and later.
D
6–9:
)
Transmitter
D.
Parallel 50 Ω with calibration
Differential
Series 25 Ω without calibration
Series 50 Ω without calibration
Series 25 Ω with calibration
Series 40 Ω with calibration
Series 50 Ω with calibration
Series 60 Ω with calibration
Dedicated clock input pairs CLK[1,3,8,10][p,n],
D
termination.
D
in row I/O banks when both V
Value
CCIO
Figure
Z
Z
O
O
and V
= 50 Ω
= 50 Ω
6–22. Differential OCT R
CCPD
is set to 2.5 V. Column I/O banks
CCIO
Input buffers for single-ended and
differential HSTL/SSTL standards
Input buffers for LVDS receivers on
row I/O banks
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
chapter.
and V
CCPD
100 Ω
Stratix IV Device Handbook Volume 1
are set to 2.5 V.
Applies To
Receiver
(1)
D
can be enabled
High Speed
6–31
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: