DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 345

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
Figure 10–3. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V
(2) The nCEO pins of both Stratix IV devices are left unconnected when configuring the same configuration data into multiple devices.
April 2011 Altera Corporation
(MAX II Device or
meet the V
Microprocessor)
External Host
ADDR DATA[7..0]
Figure
Memory
IH
10–3:
specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V
f
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
In a multi-device FPP configuration chain, all Stratix IV devices in the chain must
either enable or disable the decompression and/or design security features. You
cannot selectively enable the decompression and/or design security features for each
device in the chain because of the DATA and DCLK relationship. If the chain contains
devices that do not support design security, use a serial configuration scheme.
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave the nCEO pins floating. All other configuration
pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time.
Figure 10–3
receiving the same configuration data.
You can use a single configuration chain to configure Stratix IV devices with other
Altera devices that support FPP configuration, such as other types of Stratix devices.
To ensure that all devices in the chain complete configuration at the same time, or that
an error flagged by one device initiates reconfiguration in all devices, tie all of the
device CONF_DONE and nSTATUS pins together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
the Configuration Handbook.
V
10 kΩ
CCPGM
(1)
V
CCPGM
shows a multi-device FPP configuration when both Stratix IV devices are
10 kΩ
(1)
GND
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix IV Device
Configuring Mixed Altera FPGA Chains
MSEL[2..0]
nCEO
GND
N.C. (2)
GND
Stratix IV Device Handbook Volume 1
CCPGM
nCE
CONF_DONE
nSTATUS
DATA[7..0]
nCONFIG
DCLK
STATUS
Stratix IV Device
must be high enough to
specification.
in volume 2 of
MSEL[2..0]
nCEO
GND
N.C. (2)
10–11
CCPGM.