DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 601
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 601 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–124. Transceiver Datapath in XAUI Mode
February 2011 Altera Corporation
rx_coreclk[3:2]
tx_coreclk[1:0]
rx_coreclk[1:0]
tx_coreclk[3:2]
FPGA Fabric-Transceiver
FPGA
Fabric
Interface Clock
coreclkout
XAUI Mode Datapath
Figure 1–124
in XAUI mode.
/2
Reference
Reference
Clock
Clock
Input
Input
Compensation
Compensation
Channel 0
Channel 2
Channel 0
RX Phase
shows the ALTGX megafunction transceiver datapath when configured
Channel 1
RX Phase
Channel 3
Channel 1
FIFO
CMU1_PLL
CMU0_PLL
Channel 3
Channel 2
FIFO
Compensation
Compensation
wrclk
wrclk
TX Phase
TX Phase
FIFO
FIFO
rdclk
rdclk
serializer
serializer
Byte
De-
Byte
/2
De-
/2
wrclk
wrclk
Serializer
Serializer
Divider
CMU1
Clock
Divider
CMU0
Clock
Byte
Byte
/2
/2
rdclk
rdclk
CMU1_Channel
CMU0_Channel
Low-Speed Parallel Clock from CMU 0 Clock Divider
Decoder
8B/10B
Low-Speed Parallel Clock from CMU 0 Click Divider
Low-Speed Parallel Clock from CMU 0 Clock Divider
Decoder
Low-Speed Parallel Clock from CMU 0 Clock Divider
8B/10B
Transmitter Channel PCS
Transmitter Channel PCS
Match
Rate
FIFO
Match
FIFO
Rate
Receiver Channel PCS
Recovered Clock
Recovered Clock
Low-Speed Parallel Clock
High-Speed Serial Clock
Encoder
8B/10B
Encoder
8B/10B
Receiver Channel PCS
Ch0 Parallel
Ch0 Parallel
Stratix IV Device Handbook Volume 2: Transceivers
Deskew
Deskew
FIFO
FIFO
Aligner
Word
Aligner
Word
Receiver Channel PMA
Serializer
Transmitter Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
serializer
Recovered Clock
De-
Recovered Clock
De-
Serializer
Serializer
Ch2 Parallel
Ch0 Parallel
CDR
CDR
1–157
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