DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 496
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 496 of 1154
- Download datasheet (32Mb)
1–52
Figure 1–44. Receiver Channel Data Path showing the EyeQ Feature
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_mode_sel[3:0]
ctrl_writedata[15:0]
f
1
1
ALTGX_RECONFIG Instance
ctrl_address[15:0]
EyeQ Control
Normally, the receiver CDR samples the incoming signal at the center of the eye.
When you enable the EyeQ hardware, it allows the CDR to sample across 32 different
positions within one unit interval (UI) of a data eye. You can manually control the
sampling points and check the bit-error rate (BER) at each of these 32 sampling points.
At the center of the eye, the BER is 0. As the sampling point is moved away from the
center of the eye towards an edge, the BER increases. By observing sampling points
with 0 BER and sampling points with higher BER, you can determine the eye width.
The EyeQ hardware is available for both regular transceiver channels and CMU
channels.
The EyeQ block resides within the PMA of the receiver channel and is available for
both the transceiver channels and CMU channels of a transceiver block.
shows the EyeQ feature within a receiver channel datapath.
You must implement logic to check the bit error rate (BER). This includes a pattern
generator and checker.
Figure 1–44
For more information about using the EyeQ feature, refer to the
Reconfiguration in Stratix IV Devices
Block
ctrl_readdata[15:0]
ctrl_write
ctrl_waitrequest
ctrl_read
error
shows the receiver channel data path using the EyeQ feature.
busy
reconfig_fromgxb[17:0]
reconfig_togxb[3:0]
chapter.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Receiver Channel 0
EyeQ Hardware
ALTGX Instance
February 2011 Altera Corporation
Transceiver Block Architecture
Dynamic
Figure 1–44
rx_datain[0]
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