DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 885

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Table 5–9. tx_datainfull[43:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 2 of 2)
February 2011 Altera Corporation
20-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 10 bits
32-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 16/20 bits
40-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA set
to 20 bits
Note to
(1) For all transceiver-related ports, refer to the “Transceiver Port Lists” section in the
FPGA Fabric-Transceiver Channel
Table
Interface Description
5–9:
Two 10-bit Data (tx_datain)
tx_datainfull[9:0] - tx_datain (LSByte) and tx_datainfull[31:22] -
tx_datain (MSByte)
Four 8-bit Data (tx_datain)
tx_datainfull[7:0]- tx_datain (LSByte) and
tx_datainfull[18:11]
tx_datainfull[29:22]
tx_datainfull[40:33] - tx_datain (MSByte)
The following signals are used only in 8B/10B modes:
Four Control Bits (tx_ctrlenable)
tx_datainfull[8] - tx_ctrlenable (LSB) and
tx_datainfull[19]
tx_datainfull[30]
tx_datainfull[41]- tx_ctrlenable (MSB)
Force Disparity Enable (tx_forcedisp)
tx_datainfull[9]- tx_forcedisp (LSB) and
tx_datainfull[20]
tx_datainfull[31]
tx_datainfull[42]- tx_forcedisp (MSB)
Force Disparity Value (tx_dispval)
tx_datainfull[10]- tx_dispval (LSB) and
tx_datainfull[21]
tx_datainfull[32]
tx_datainfull[43]- tx_dispval (MSB)
Four 10-bit Data (tx_datain)
tx_datainfull[9:0] - tx_datain (LSByte) and
tx_datainfull[20:11]
tx_datainfull[31:22]
tx_datainfull[42:33]- tx_datain (MSByte)
Transmit Signal Description (Based on Stratix IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
Transceiver Architecture for Stratix IV Devices
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
(Note 1)
5–39