DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 302
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 302 of 1154
- Download datasheet (32Mb)
8–24
Figure 8–19. Receiver Datapath in DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–19:
10
DPA Mode
Figure 8–19
in
best possible clock (DPA_diffioclk) from the eight fast clocks sent by the left and right
PLL. This serial DPA_diffioclk clock is used for writing the serial data into the
synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from
the synchronizer. The same LVDS_diffioclk clock is used in data realignment and
deserializer blocks.
IOE Supports SDR, DDR, or Non-Registered Datapath
“Receiver Hardware Blocks” on page 8–19
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the DPA mode datapath, where all the hardware blocks mentioned
IOE
2
Left/Right PLL
(Note
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
1), (2),
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
diffioclk
(3)
rx_inclock
are active. The DPA block chooses the
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
February 2011 Altera Corporation
Retimed
Data
DPA Clock
DPA Circuitry
DIN
Differential Receiver
+
LVDS Clock Domain
DPA Clock Domain
rx_in
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