DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 498

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–54
Stratix IV Device Handbook Volume 2: Transceivers
f
1
You can drive the receiver input reference clock with the following clock sources:
■
■
■
■
Table 1–24
Table 1–24. CDR Divider Values
For input reference clock frequencies greater than 325 MHz, the Quartus II software
automatically selects the appropriate /1, /2, or /4 pre-divider to meet the PFD input
frequency limitation of 325 MHz.
The CDR must be in LTD mode to recover the clock from the incoming serial data
during normal operation. In LTD mode, the phase detector (PD) in the CDR tracks the
incoming serial data at the receiver buffer. Depending on the phase difference
between the incoming data and the CDR output clock, the PD controls the CDR
charge pump that tunes the VCO.
(in red) when the CDR is in LTD mode.
The PFD is inactive in LTD mode. The rx_pll_locked signal toggles randomly and
has no significance in LTD mode.
After switching to LTD mode, it can take a maximum of 1 ms for the CDR to get
locked to the incoming data and produce a stable recovered clock. The actual lock
time depends on the transition density of the incoming data and the PPM difference
between the receiver input reference clock and the upstream transmitter reference
clock. The receiver PCS logic must be held in reset until the CDR produces a stable
recovered clock.
For more information about receiver reset recommendations, refer to the
and Power Down in Stratix IV Devices
/M Divider
/L Divider
Note to
(1) The maximum reference clock frequency of 672 MHz is only applicable to speed grades -2 and -3. For speed grade
Dedicated REFCLK pins (refclk0 and refclk1) of the associated transceiver block
Inter-transceiver block (ITB) clock lines from other transceiver blocks on the same
side of the device (up to six ITB clock lines, two from each transceiver block)
Global PLD clock driven by a dedicated clock input pin
Clock output from the left and right PLLs in the FPGA fabric
Lock-to-Data (LTD) Mode
-4, the maximum reference clock frequency is 637.5 MHz.
Table
lists CDR /M and/L divider values.
Parameter
1–24:
Figure 1–45 on page 1–53
chapter.
Chapter 1: Transceiver Architecture in Stratix IV Devices
4, 5, 8, 10, 16, 20, 25
1, 2, 4, 8
Value
shows the active blocks
February 2011 Altera Corporation
Transceiver Block Architecture
Reset Control