DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 280

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

8–2
Figure 8–1. I/O Bank Support in the Stratix IV Device Family
Notes to
(1) Column input buffers are true LVDS buffers, but do not support 100-Ω differential on-chip termination.
(2) Column output buffers are single ended and need external termination schemes to support LVDS, mini-LVDS, and RSDS standards. For more
(3) Row input buffers are true LVDS buffers and support 100-Ω differential on-chip termination.
(4) Row output buffers are true LVDS buffers.
Stratix IV Device Handbook Volume 1
information, refer to the
Figure
with 'Use External PLL'
Option Enabled
LVDS Interface
8–1:
■
■
■
■
For high-speed differential interfaces, the Stratix IV device family supports the
following differential I/O standards:
■
■
■
In the Stratix IV device family, I/Os are divided into row and column I/Os.
shows I/O bank support for the Stratix IV device family. The row I/Os provide
dedicated SERDES circuitry.
I/O Features in Stratix IV Devices
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs) (located on left and right sides of the device)
LVDS
Mini-LVDS
Reduced swing differential signaling (RSDS)
SERDES Circuitry (3), (4)
Row I/Os with
Dedicated
chapter.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
with 'Use External PLL'
Option Disabled
LVDS Interface
(Note
LVDS I/Os
1), (2), (3),
(4)
February 2011 Altera Corporation
Column I/Os (1), (2)
Figure 8–1
Overview