DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 844

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–38
Power Down
Figure 4–22. Sample Reset Sequence of Four Receiver and Transmitter Channels-Receiver CDR in Automatic Lock Mode
with the Optional gxb_powerdown Signal
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Reset/Power Down Signals
Output Status Signals
Figure
gxb_powerdown
LTD_Auto
gxb_powerdown
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
4–22:
duration, refer to the
pll_locked
duration, refer to the
busy
5. After assertion of the channel_reconfig_done signal, de-assert tx_digitalreset
6. Lastly, wait for the rx_freqlocked signal to go high. After rx_freqlocked goes
The Quartus II software automatically selects the power-down channel feature, which
takes effect when you configure the Stratix IV device. All unused transceiver channels
and blocks are powered down to reduce overall power consumption. The
gxb_powerdown signal is an optional transceiver block signal. It powers down all
transceiver channels and all functional blocks in the transceiver block. The minimum
pulse width for this signal is 1 μs. After power up, if you use the gxb_powerdown
signal, wait for de-assertion of the busy signal, then assert the gxb_powerdown signal
for a minimum of 1 μs. Lastly, follow the sequence shown in
The de-assertion of the busy signal indicates proper completion of the offset
cancellation process on the receiver channel.
(marker 5) and wait for at least five parallel clock cycles to de-assert the
rx_analogreset signal (marker 6).
high (marker 7), wait for t
(marker 8). At this point, the receiver is ready for data traffic.
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
1
t
gxb_powerdown (1)
LTD_Auto
3
to de-assert the rx_digitalreset signal
Chapter 4: Reset Control and Power Down in Stratix IV Devices
4
5
chapter.
6
chapter.
Figure
February 2011 Altera Corporation
7
t
4–22.
LTD_Auto (2)
8
Power Down