DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 173

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SIV51006-3.2
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51006-3.2
This chapter describes how Stratix
you to work in compliance with current and emerging I/O standards and
requirements. With these device features, you can reduce board design interface costs
and increase development flexibility.
Altera
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV I/Os are specifically designed for ease-of-use and rapid
system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and produce system-level performance.
Stratix IV device I/O capability far exceeds the I/O bandwidth available from
previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/O.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■
■
■
■
■
■
■
■
■
■
■
■
■
Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 8.5 Gbps
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express
(GbE), Serial RapidIO
SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, data link layer, and transaction layer functionality
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signaling
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
Up to 132 full duplex 1.6 Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
Deskew, read and write leveling, and clock-domain crossing functionality
Programmable output current strength
Programmable slew rate
Programmable delay
Programmable bus-hold circuit
®
Stratix IV FPGAs deliver a breakthrough level of system bandwidth and
®
, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G,
6. I/O Features in Stratix IV Devices
®
®
(PIPE) (PCIe) Gen1 and Gen2, Gigabit Ethernet
IV devices provide I/O capabilities that allow
Subscribe