DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 219
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 219 of 1154
- Download datasheet (32Mb)
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
February 2011 Altera Corporation
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one
V
number of input signals with different I/O standard assignments if it meets the V
and V
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as V
V
For example, an I/O bank with a 2.5-V V
inputs and outputs as well as 3.0-V LVCMOS inputs (but not output or bidirectional
pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix IV device’s I/O bank
supports multiple VREF pins feeding a common V
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as generic I/O pins and must be tied to V
can only have a single V
time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same V
setting.
For performance reasons, voltage-referenced input standards use their own V
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a V
HSTL-15 input pins in an I/O bank with 2.5-V V
input with parallel OCT enabled requires the V
voltage of the input standard.
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s V
bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
CCIO
CCIO
, either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any
CCPD
value, it can only drive out that one value for non-voltage-referenced signals.
CCIO
requirement, as shown in
voltage. For example, you can only place SSTL-2 output pins in an I/O
CCIO
.
CCIO
voltage level and a single V
CCIO
of 2.5 V or below. For example, you can place
Table 6–2 on page
CCIO
CCIO
. Because an I/O bank can only have one
setting can support 2.5-V standard
CCIO
CCIO
REF
. However, the voltage-referenced
of the I/O bank to match the
bus. The number of available
CCIO
6–3.
REF
and 0.75-V V
Stratix IV Device Handbook Volume 1
voltage level at a given
CCIO
CCIO
and a 0.9-V V
or GND. Each bank
REF
.
CCPD
REF
REF
.
CCIO
6–47
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