DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 637
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 637 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–157. Reverse Serial Loopback Datapath (Grayed-Out Blocks are Not Active in this Mode)
February 2011 Altera Corporation
Fabric
FPGA
RX Phase
Compen-
sation
FIFO
Reverse Serial Loopback
Reverse serial loopback is available as a subprotocol under Basic functional mode. In
reverse serial loopback mode, the data is received through the rx_datain port,
retimed through the receiver CDR and sent out to the tx_dataout port. The received
data is also available to the FPGA logic. No dynamic pin control is available to select
or deselect reverse serial loopback.
datapath for reverse serial loopback mode.
The active block of the transmitter channel is only the transmitter buffer. You can
change the output differential voltage and the pre-emphasis first post tap values on
the transmitter buffer through the ALTGX MegaWizard Plug-In Manager or through
the dynamic reconfiguration controller. Reverse serial loopback is often implemented
when using a bit error rate tester (BERT) on the upstream transmitter.
TX Phase
Compen-
Ordering
sation
FIFO
Byte
Serialzier
De-Serializer
Byte
Byte
Encoder
8B/10B
8B/10B
Decoder
Figure 1–157
Transmitter Channel PCS
Receiver Channel PCS
shows the transceiver channel
Aligner
Stratix IV Device Handbook Volume 2: Transceivers
Word
Loopback
Reverse
Serializer
Serial
Transmitter Channel PMA
Receiver Channel PMA
De-
Serializer
Receiver
CDR
1–193
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