DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 353

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Active Serial Configuration (Serial Configuration Devices)
April 2011 Altera Corporation
1
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
When the Stratix IV device is in user mode, you can initiate reconfiguration by pulling
the nCONFIG pin low. The nCONFIG pin must be low for at least 2 μs. When nCONFIG is
pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released by the
Stratix IV device, reconfiguration begins.
If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the
nCE pin high. This causes the device to reset and tri-state the AS configuration pins.
The timing parameters for AS mode are not listed here because the t
t
for PS mode listed in
You can configure multiple Stratix IV devices using a single serial configuration
device. You can cascade multiple Stratix IV devices using the chip-enable (nCE) and
chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin
connected to GND. You must connect its nCEO pin to the nCE pin of the next device in
the chain. When the first device captures all of its configuration data from the
bitstream, it drives the nCEO pin low, enabling the next device in the chain. You must
leave the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS, CONF_DONE,
DCLK, and DATA0 pins of each device in the chain are connected (refer to
The first Stratix IV device in the chain is the configuration master and controls
configuration of the entire chain. You must connect its MSEL pins to select the AS
configuration scheme. The remaining Stratix IV devices are configuration slaves. You
must connect their MSEL pins to select the PS configuration scheme. Any other Altera
device that supports PS configuration can also be part of the chain as a configuration
slave.
STATUS
, t
CF2ST1
, and t
CD2UM
Table 10–7 on page
timing parameters are identical to the timing parameters
10–30.
Stratix IV Device Handbook Volume 1
STATUS
CF2CD
specification.
Figure
, t
CF2ST0
10–7).
, t
10–19
CFG
,