DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 525

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–64. Rate Match Deletion in XAUI Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
Before Rate Match:
After Rate Match:
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
datain[2]
datain[1]
datain[0]
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the
four channels goes high for one clock cycle per deleted ||R|| column. If an ||R||
column is inserted, the rx_rmfifoinserted flag from each of the four channels goes
high for one clock cycle per inserted ||R|| column.
Figure 1–64
columns must be deleted.
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
shows an example of rate match deletion in the case where three ||R||
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
First ||R||
Column
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
Second ||R||
Column
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
Stratix IV Device Handbook Volume 2: Transceivers
Third ||R||
Column
K28.0
K28.0
K28.0
K28.0
Fourth ||R||
Column
K28.0
K28.0
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
1–81