DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1028

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Compilation
Compilation
February 2011 Altera Corporation
When you compile your design, the Quartus II software generates an SRAM Object
File (.sof) or programmer object file (.pof) that you can download to the Stratix IV GX
hardware. Typically, the first step in compiling the design is assigning pin locations
for the I/Os and clocks. Use the pin planner tool in the Quartus II software to assign
pins.
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The Quartus II software generates multiple report files that contain information such
as transceiver configuration and clock resource utilization. The following section
describes the report files relevant to using transceivers and clock resource.
1
Stratix IV GX transceivers support a variety of I/O standards for the input
reference clocks and serial data pins. Assign pins and the logic level standard (for
example, 1.5-V PCML and LVDS) for the input and output pins.
f
If you share the same transceiver-FPGA fabric interface clocks for multiple
transceiver channels (tx_coreclk and rx_coreclk) in your design, set the 0 ppm
constraints. These constraints enable the Quartus II software to relax the legality
check restrictions on clocking.
f
For transceiver serial pins and refclk pins, set the on-chip termination (OCT)
resistor settings.
f
Create timing constraints for the clocks and data paths. Use the TimeQuest Timing
Analyzer to set timing constraints.
f
Compile the design. This generates a .sof that can be downloaded in the FPGA.
For a basic tutorial about the Quartus II software, open the Quartus II
software, click the Help menu and select Tutorial.
For more information, refer to the
For more information, refer to the “Common Clock Driver Selection Rules”
section of the
For more information about supported OCT settings, refer to “Transmitter
Output Buffer” section of the
chapter.
For more information about the TimeQuest Timing Analyzer, refer to the
Quartus II Development Software
Transceiver Clocking in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Handbook.
I/O Features in Stratix IV Devices
Stratix IV Device Handbook Volume 3
chapter.
chapter.
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