DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 421

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices
BST Operation Control
Table 12–2. IDCODE Information for Stratix IV Devices (Part 2 of 2)
February 2011 Altera Corporation
Notes to
(1) The MSB is on the left.
(2) The LSB of the IDCODE is always 1.
(3) The IDCODE is applicable for all packages except F1932.
(4) The IDCODE is applicable for package F1932 only.
(5) For the ES1 device, the IDCODE is the same as the IDCODE of EP4SGX230.
(6) For the ES1 device, the IDCODE is the same as the IDCODE of EP4SGX530.
EP4S100G2
EP4S100G5
EP4S40G2
EP4S40G5
EP4S100G3
EP4S100G4
EP4SE530
EP4SE820
Table
Device
12–2:
f
1
(5)
(6)
(5)
(6)
If the device is in reset state, when the nCONFIG or nSTATUS signal is low, the device
IDCODE might not be read correctly. To read the device IDCODE correctly, you must
issue the IDCODE JTAG instruction only when the nSTATUS signal is high.
For more information about the following topics, refer to the
Boundary-Scan Testing in Stratix III Devices
Handbook:
■
■
■
■
■
■
JTAG instruction codes with descriptions
TAP controller state-machine
Timing requirements for IEEE Std. 1149.1 signals
Instruction mode
Mandatory JTAG instructions (SAMPLE/PRELOAD, EXTEST, and BYPASS)
Optional JTAG instructions (IDCODE, USERCODE, CLAMP, and HIGHZ)
Version (4 Bits)
0000
0000
0000
0000
0000
0000
0000
0000
Part Number (16 Bits)
0010 0100 0001 0011
0010 0100 0000 0100
0010 0100 0100 0001
0010 0100 0010 0011
0010 0100 0100 0001
0010 0100 1010 0011
0010 0100 0110 0011
0010 0100 0010 0011
IDCODE (32 Bits)
chapter in volume 1 of the Stratix III Device
(1)
Manufacturer Identity
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
Stratix IV Device Handbook Volume 1
(11 Bits)
IEEE 1149.1 (JTAG)
(1 Bit)
LSB
1
1
1
1
1
1
1
1
12–3
(2)