DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 814

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–8
Figure 4–4. Sample Reset Sequence for Four Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Output Status Signals
Figure
pll_powerdown
LTD_Auto
Reset Signals
pll _ powerdown
rx _analogreset
rx_freqlocked[0]
rx_freqlocked[3]
tx _digitalreset
rx _digitalreset
4–4:
duration, refer to the
pll
_
locked
duration, refer to the
busy
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in automatic lock mode, use the reset
sequence shown in
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
2
3
4
Figure
Minimum of Two Parallel Clock Cycles
5
4–4.
6
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
t
LTD_Auto (2)
chapter.
chapter.
8
February 2011 Altera Corporation
Transceiver Reset Sequences