DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 216
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 216 of 1154
- Download datasheet (32Mb)
6–44
Stratix IV Device Handbook Volume 1
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage.
AC-coupled termination scheme. The 50-
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification
Figure 6–33. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Figure
Figure
LVPECL Output Buffer
LVPECL Output Buffer
6–32:
6–33:
Altera FPGA
Altera FPGA
0.1 μF
0.1 μF
Z
Z
Z
Z
O
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
= 50 Ω
Ω
(Note 1)
(Note 1)
resistors used at the receiver end are
V
ICM
100 Ω
Chapter 6: I/O Features in Stratix IV Devices
Figure 6–32
(Figure
50 Ω
50 Ω
Termination Schemes for I/O Standards
Stratix IV LVPECL
February 2011 Altera Corporation
Stratix IV LVPECL
Input Buffer
6–33).
Input Buffer
shows the
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