DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 76

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–20
Stratix IV Device Handbook Volume 1
f
Figure 3–18
behavior in old data mode for M9K and M144K blocks.
Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock.
In this mode, you also have two output choices: “old data” or “don’t care”. In old data
mode, a read-during-write operation to different ports causes the RAM outputs to
reflect the “old data” at that address location. In don’t care mode, the same operation
results in a “don’t care” or “unknown” value on the RAM outputs.
Read-during-write behavior is controlled with the RAM MegaWizard Plug-In
Manager. For more information, refer to the
Guide.
Figure 3–19
behavior for old data mode in MLABs.
Figure 3–19. MLABs Mixed-Port Read-During-Write: Old Data Mode
q_b(registered)
q_a (asyn)
wraddress
rdaddress
byteena_a
address
bytenna
data_in
data_a
wrena
wrena
clk_a
rdena
clk_a
shows sample functional waveforms of same-port read-during-write
shows a sample functional waveform of mixed-port read-during-write
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
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old
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old
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Internal Memory (RAM and ROM) User
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February 2011 Altera Corporation
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Design Considerations
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