DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 66
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 66 of 1154
- Download datasheet (32Mb)
3–10
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Stratix IV Device Handbook Volume 1
8K × 1
4K × 2
2K × 4
Read Port
Simple Dual-Port Mode
Figure 3–8
mode with unregistered outputs. Registering the RAM’s outputs simply delays the
q output by one clock cycle.
Figure 3–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode
allows you to perform one read and one write operation to different locations at the
same time. Write operation happens on port A; read operation happens on port B.
Figure 3–9
Figure 3–9. Stratix IV Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input/output clock mode in addition to read/write clock mode.
Simple dual-port mode supports different read and write data widths (mixed-width
support).
dual-port mode. MLABs do not have native support for mixed-width operation. The
Quartus II software implements mixed-width memories in MLABs by using more
than one MLAB.
8K × 1
v
v
v
q_a (asyn)
Figure
address
bytenna
data_a
wrena
clk_a
rdena
4K × 2
Table 3–5
v
v
v
shows timing waveforms for read and write operations in single-port
shows a simple dual-port configuration.
3–9:
2K × 4
lists the mixed width configurations for M9K blocks in simple
v
v
v
A123
01
A0 (old data)
1K × 8
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
v
v
v
B456
10
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
A0
D
512 × 16
old
Write Port
v
v
v
D
old
23
C789
00
(Note 1)
B423
256 × 32
rd_addressstall
v
v
v
rdaddress[ ]
ecc_status
rdclocken
DDDD
rdclock
rden
A1(old data)
q[ ]
1K × 9
—
—
—
February 2011 Altera Corporation
A1
EEEE
11
DDDD
512 × 18
—
—
—
FFFF
Memory Modes
EEEE
256 × 36
—
—
—
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