DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1047

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
Figure 2–12. FC4G Instance Settings (Word Aligner Screen)
February 2011 Altera Corporation
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Word Aligner screen—The fibre channel protocol requires that you use K28.5 to
align the byte boundary. In the What is the word alignment pattern? option, set
one of the 10-bit disparity values to K28.5. The word aligner automatically detects
when the other disparity value is received.
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Select the rx_patterndetect and rx_syncstatus signals. The
rx_patterndetect signal indicates whenever the word alignment pattern is
detected in the word boundary.
Click Finish to exit the ALTGX MegaWizard Plug-In Manager.
Stratix IV Device Handbook Volume 3
2–29