DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 651
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 651 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Built-In Self Test Modes
Figure 1–174. BIST PRBS, High Frequency, and Low Frequency Pattern Datapath
Table 1–71. Available PRBS, High Frequency, and Low Frequency Patterns in Single-Width Mode
February 2011 Altera Corporation
Patterns
PRBS 7
PRBS 8
PRBS 10
PRBS 23
High
frequency
(2)
FPGA
Fabric
PRBS in Single-Width Mode
Compen-
Polynomial
Phase
Compen-
sation
X
1010101010
FIFO
Phase
X
sation
TX
FIFO
X
X
RX
23
10
7
8
+ X
+ X
+ X
+ X
Different PRBS patterns are available as a subprotocol under Basic functional mode
for single-width and double-width mode, as shown in the following sections.
You can enable the serial loopback option in Basic PRBS mode to loop the generated
pattern to the receiver channel. This creates a rx_seriallpbken port that you can use
to dynamically control the serial loopback. The 8B/10B encoder/decoder blocks are
bypassed in Basic PRBS mode.
Figure 1–174
sent to the transmitter serializer. The verifier checks the data from the word aligner.
Table 1–71
patterns for PRBS in single-width mode configuration.
6
7
18
7
+ 1
+ 1
+ 1
+ 1
Ordering
Byte
Serializer
Byte
Width of
8 Bit
Channel
lists the various PRBS patterns and corresponding word alignment
N
Y
Y
Y
Y
serializer
shows the datapath for the PRBS patterns. The generated PRBS pattern is
Byte
De-
(1)
Encoder
8B/10B
BIST PRBS, High-Freq,
Pattern with
Width 8 Bit
Low-Freg pattern
Alignment
Receiver Channel PCS
16’h3040
16’hFF5A
Decoder
16’hFFFF
8B/10B
Channel
generator
Word
NA
NA
Width 8 Bit
Match
FIFO
Rate
Maximum
Data Rate
Channel
(Gbps)
Transmitter Channel PCS
With
N/A
2.5
2.5
2.5
2.5
BIST PRBS verifier
Deskew
FIFO
10 Bit
Width of
Stratix IV Device Handbook Volume 2: Transceivers
Channel
Aligner
Word
N
N
N
Y
Y
(1)
serializer
Receiver Channel
Serializer
Transmitter Channel PMA
De-
Alignment
PMA
Pattern
10’h3FF
Word
Receiver
NA
NA
NA
NA
CDR
can be dynamically enabled
Width 10 Bit
Serial loop back
Data Rate
Maximum
Channel
(Gbps)
3.125
3.125
with
N/A
N/A
N/A
1–207
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: