DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 290
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 290 of 1154
- Download datasheet (32Mb)
8–12
Stratix IV Device Handbook Volume 1
The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at
serial data rate) generated from PLL_Lx (left PLL) or PLL_Rx (right PLL) clocks the load
and shift registers. You can statically set the serialization factor to ×3, ×4, ×6, ×7, ×8, or
×10 using the Quartus II software. The load enable signal is derived from the
serialization factor setting.
transmitter.
Figure 8–5. Stratix IV Transmitter
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
You can configure any Stratix IV transmitter data channel to generate a
source-synchronous transmitter clock output. This flexibility allows the placement of
the output clock near the data outputs to simplify board layout and reduce
clock-to-data skew. Different applications often require specific clock-to-data
alignments or specific data-rate-to-clock-rate factors. The transmitter can output a
clock signal at the same rate as the data with a maximum frequency of 800 MHz. The
output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the
serialization factor. You can set the phase of the clock in relation to the data at 0° or
180° (edge or center aligned). The left and right PLLs (PLL_Lx and PLL_Rx) provide
additional support for other phase shifts in 45° increments. These settings are made
statically in the Quartus II MegaWizard Plug-In Manager software.
tx_coreclock
Figure
Fabric
FPGA
tx_in 10
8–5:
Left/Right PLL
DIN
Serializer
3
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Figure 8–5
2
(Note
IOE
1),
tx_inclock
shows a block diagram of the Stratix IV
(2)
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
February 2011 Altera Corporation
LVDS Clock Domain
Differential Transmitter
+
-
tx_out
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