DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 613

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–135. Reset Condition in GIGE Mode
February 2011 Altera Corporation
tx_digitalreset
tx_dataout
clock
After de-assertion of tx_digitalreset, the GIGE transmitter automatically transmits
three /K28.5/ comma code groups before transmitting user data on the tx_datain
port. This could affect the synchronization state machine behavior at the receiver.
Depending on when you start transmitting the synchronization sequence, there could
be an even or odd number of /Dx.y/ code groups transmitted between the last of the
three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the
synchronization sequence. If there is an even number of /Dx.y/ code groups received
between these two /K28.5/ code groups, the first /K28.5/ code group of the
synchronization sequence begins at an odd code group boundary (rx_even = FALSE).
An IEEE802.3-compliant GIGE synchronization state machine treats this as an error
condition and goes into the loss of sync state.
Figure 1–135
automatically sent /K28.5/ and the first user-sent /K28.5/. The first user-sent
/K28.5/ code group received at an odd code group boundary in cycle n + 3 takes the
receiver synchronization state machine in the loss of sync state. The first
synchronization ordered set /K28.5/Dx.y/ in cycles n + 3 and n + 4 is discounted and
three additional ordered sets are required for successful synchronization.
The word aligner in GIGE functional mode is configured in automatic
synchronization state machine mode. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization when the
receiver receives three consecutive synchronization ordered sets. A synchronization
ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code
groups. The fastest way for the receiver to achieve synchronization is to receive three
continuous {/K28.5/, /Dx.y/} ordered sets.
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized; a low on the
rx_syncstatus port indicates that the lane has fallen out of synchronization. The
receiver loses synchronization when it detects four invalid code groups separated by
less than three valid code groups or when it is reset.
K28.5
Reset Condition
Word Aligner
xxx
shows an example of even numbers of /Dx.y/ between the last
K28.5
K28.5
K28.5
n
n + 1
Dx.y
n + 2
Dx.y
n + 3 n + 4
K28.5
Dx.y
Stratix IV Device Handbook Volume 2: Transceivers
K28.5
Dx.y
K28.5
Dx.y
1–169