DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 714

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–42
Figure 2–24. Receiver Datapath Clocking in Non-Bonded Configurations with Rate Matcher
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, the dark red lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the parallel recovered clock, and the blue lines represent the serial recovered clock.
rx_coreclk[0]
rx_coreclk[2]
rx_coreclk[3]
rx_coreclk[1]
Figure
Fabric
FPGA
2–24:
FPGA Fabric_Transceiver
FPGA Fabric_Transceiver
FPGA Fabric_Transceiver
FPGA Fabric_Transceiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
Figure 2–24
configurations with rate matcher.
In non-bonded configurations with rate matcher, the CDR in each receiver channel
recovers the serial clock from the received data. The serial recovered clock is divided
within the receiver PMA to generate the parallel recovered clock. The deserializer
uses the serial recovered clock in the receiver PMA. The parallel recovered clock and
deserialized data are forwarded to the receiver PCS.
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
Interface
Interface
Interface
Interface
tx_clkout[2]
tx_clkout[1]
tx_clkout[0]
PIPE
tx_clkout[3]
PIPE
PIPE
PIPE
shows the receiver datapath clocking in non-bonded channel
Compensation
Compensation
Compensation
Compensation
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
Ordering
Ordering
Ordering
Ordering
Byte
Byte
Byte
Byte
Serializer
Serializer
Serializer
Serializer
Byte
Byte
/2
De-
/2
Byte
/2
Byte
/2
De-
De-
De-
Decoder
Decoder
Decoder
Decoder
8B/10B
8B/10B
8B/10B
8B/10B
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Chapter 2: Transceiver Clocking in Stratix IV Devices
Match
Match
Match
Match
Rate
FIFO
FIFO
Rate
FIFO
Rate
FIFO
Rate
Recovered Clock
Recovered Clock
Recovered Clock
Recovered Clock
Ch2 Parallel
Ch3 Parallel
Ch1 Parallel
Ch0 Parallel
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Channel 3
Channel 1
Channel 0
Channel 2
Transceiver Channel Datapath Clocking
Serializer
Serializer
Receiver Channel PMA
Serializer
Receiver Channel PMA
Serializer
Receiver Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
De-
Divider
De-
Divider
De-
Divider
De-
Divider
Clock
Local
Clock
Local
Clock
Local
Clock
Local
February 2011 Altera Corporation
(Note 1)
CDR
From CMU0 PLL
From CMU1 PLL
From CMU0 PLL
From CMU1 PLL
CDR
CDR
From CMU0 PLL
From CMU1 PLL
Serial Recovered Clock
CDR
From CMU0 PLL
From CMU1 PLL
Serial Recovered Clock
Serial Recovered Clock
Serial Recovered Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock
Input Reference Clock