DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 508

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–64
Table 1–28. Synchronization State Machine Functional Modes
Stratix IV Device Handbook Volume 2: Transceivers
Number of valid synchronization code groups or
ordered sets received to achieve
synchronization
Number of erroneous code groups received to
lose synchronization
Number of continuous good code groups
received to reduce the error count by one
1
Functional Mode
In Basic single-width functional mode with a 10-bit PMA-PCS interface, you can
configure the word aligner in automatic synchronization state machine mode by
selecting the Use the built-in synchronization state machine option in the ALTGX
MegaWizard Plug-In Manager. It also allows you to program a custom 7-bit or 10-bit
word alignment pattern that the word aligner uses for synchronization.
The 10-bit input data to the word aligner configured in automatic synchronization
state machine mode must be 8B/10B encoded.
Table 1–28
software allows in supported functional modes. The synchronization state machine
parameters are fixed for PCIe, XAUI, GIGE, and Serial RapidIO modes as specified by
the respective protocol. For Basic single-width mode, you can program these
parameters as suited to your proprietary protocol implementation.
After de-assertion of the rx_digitalreset signal in automatic synchronization state
machine mode, the word aligner starts looking for the word alignment pattern or
synchronization code groups in the received data stream. When the programmed
number of valid synchronization code groups or ordered sets is received, the
rx_syncstatus signal is driven high to indicate that synchronization is acquired. The
rx_syncstatus signal is constantly driven high until the programmed number of
erroneous code groups is received without receiving intermediate good groups; after
which the rx_syncstatus is driven low. The word aligner indicates loss of
synchronization (rx_syncstatus remains low) until the programmed number of valid
synchronization code groups are received again.
In Basic single-width mode with a 10-bit PMA-PCS interface, you can configure the
word aligner in manual alignment mode by selecting the Use manual word
alignment mode option in the ALTGX MegaWizard Plug-In Manager.
In manual alignment mode, the word aligner operation is controlled by the input
signal rx_enapatternalign. The word aligner operation is level-sensitive to the
rx_enapatternalign signal. If the rx_enapatternalign signal is held high, the word
aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the
received data stream. It updates the word boundary if it finds the word alignment
pattern in a new word boundary. If the rx_enapatternalign signal is de-asserted low,
the word aligner maintains the current word boundary even when it sees the word
alignment pattern in a new word boundary.
Manual Alignment Mode Word Aligner with 10-Bit PMA-PCS Interface Mode
lists the synchronization state machine parameters that the Quartus II
PCIe
17
16
4
XAUI
4
4
4
Chapter 1: Transceiver Architecture in Stratix IV Devices
GIGE
3
4
4
February 2011 Altera Corporation
RapidIO
Serial
127
255
3
Transceiver Block Architecture
Single-Width
1 to 256
1 to 256
1 to 64
Basic
Mode