DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 308
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 308 of 1154
- Download datasheet (32Mb)
8–30
Stratix IV Clocking
Figure 8–23. LVDS/DPA Clocks in the Stratix IV Device Family with Center PLLs
Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs
Stratix IV Device Handbook Volume 1
2
4
4
2
4
4
4
2
2
4
4
2
2
4
The left and right PLLs feed into the differential transmitter and receive channels
through the LVDS and DPA clock network. The center left and right PLLs can clock
the transmitter and receive channels above and below them. The corner left and right
PLLs can drive I/Os in the banks adjacent to them.
Figure 8–23
information about PLL clocking restrictions, refer to
Guidelines” on page
Figure 8–24
more information about PLL clocking restrictions, refer to
Guidelines” on page
LVDS
Clock
LVDS
Clock
LVDS
LVDS
Clock
Clock
PLL_L2
PLL_L3
Center
Center
PLL_L2
PLL_L3
PLL_L4
Center
Center
Corner
Corner
PLL_L1
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
shows center PLL clocking in the Stratix IV device family. For more
shows center and corner PLL clocking in the Stratix IV device family. For
8–38.
8–38.
Quadrant
Quadrant
Quadrant
Quadrant
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Quadrant
Quadrant
Quadrant
Quadrant
“Differential Pin Placement
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
PLL_R1
PLL_R2
PLL_R3
PLL_R2
PLL_R3
PLL_R4
“Differential Pin Placement
Corner
Center
Center
Corner
Center
Center
February 2011 Altera Corporation
LVDS
Clock
LVDS
Clock
LVDS
Clock
LVDS
Clock
4
4
4
2
2
4
2
2
4
4
2
4
2
4
Stratix IV Clocking
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