DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 544

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–100
Figure 1–87. CMU Channels in a Transceiver Block
Notes to
(1) Clocks are provided to support bonded channel functional mode.
(2)
Stratix IV Device Handbook Volume 2: Transceivers
For more information, refer to the
Figure
CMU Channel Architecture
Input Reference
Input Reference
1–87:
Clocks (2)
Clocks (2)
An optional rx_phase_comp_fifo_error port is available in all functional modes to
indicate a receiver phase compensation FIFO under-run or overflow condition. The
rx_phase_comp_fifo_error signal is asserted high when the phase compensation
FIFO gets either full or empty. This feature is useful to verify a phase compensation
FIFO under-run or overflow condition as a probable cause of link errors.
Stratix IV GX and GT devices contain two CMU channels—CMU0 and CMU1—within
each transceiver block that you can configure as a transceiver channel or as a clock
generation block. In addition, each CMU channel contains a CMU PLL that provides
clocks to the transmitter channels within the same transceiver block.
Figure 1–87
Receiver Phase Compensation FIFO Error Flag
Stratix IV Transceiver Clocking
To Transmitter PMA
To Transmitter PMA
To Transmitter PCS
To Transmitter PCS
shows the two CMU channels in a transceiver block.
Low-Speed Parallel Clock
High-Speed Serial Clock
High-Speed Serial Clock
Low-Speed Parallel Clock
High-speed serial clock from xN bottom
High-speed serial clock from xN bottom
Low-speed parallel clock from xN bottom
Transmitter Channel 0
High-speed serial clock from xN top
High-speed serial clock from xN top
Low-speed parallel clock from xN top
Low-speed parallel clock from xN bottom
Low-speed parallel clock from xN top
Transmitter Channel 2
CMU1 Channel
chapter.
CMU0 Channel
Transmitter Channel 1
Transmitter Channel 3
Stratix IV GX Transceiver Block
Local Clock
Local Clock
Divider
Divider
Block
Block
Chapter 1: Transceiver Architecture in Stratix IV Devices
PARALLEL Clock (1)
High-Speed Clock
SERIAL Clock (1)
High-Speed Clock
High-Speed
CMU0 PLL
CMU1 PLL
Low-Speed
February 2011 Altera Corporation
Transceiver Block Architecture