DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 486

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–42
Stratix IV Device Handbook Volume 2: Transceivers
1
1
Programmable Differential On-Chip Termination
The Stratix IV GX and GT receiver buffers support optional differential OCT resistors
of 85, 100, 120, and 150 Ω . To select the desired receiver OCT resistor, make the
assignments shown in
Table 1–18. Stratix IV GX and GT Receiver On-Chip Termination Assignment Settings
The Stratix IV GX and GT receiver OCT resistors have calibration support to
compensate for process, voltage, and temperature variations. For more information
about OCT calibration support, refer to
The Stratix IV GX and GT receiver buffers have on-chip biasing circuitry to establish
the required V
that you can select in the ALTGX MegaWizard Plug-In Manager.
You must select 0.82 V as the receiver buffer V
buffer I/O standards:
■
■
■
■
You must select 1.1 V as the receiver buffer V
I/O standard.
On-chip biasing circuitry is effective only if you select on-chip receiver termination.
If you select external termination, you must implement off-chip biasing circuitry to
establish the V
A high-speed serial link can either be AC-coupled or DC-coupled, depending on the
serial protocol being implemented. Most of the serial protocols require links to be
AC-coupled, but protocols such as Common Electrical I/O (CEI) optionally allow DC
coupling.
Assignment Name
Stratix IV GX Available Values
Stratix IV GT Available Values
1.4-V PCML
1.5-V PCML
2.5-V PCML
LVPECL
Programmable V
Link Coupling for Stratix IV GX Devices
Assign To
CM
CM
at the receiver input. It supports V
at the receiver input buffer.
CM
Table 1–18
Input Termination
OCT 85 Ω , OCT 100 Ω , OCT 120 Ω, OCT 150 Ω , Off
OCT 85 Ω ,OCT 100 Ω , OCT 120 Ω , OCT 150 Ω , Off
in the Quartus II software Assignment Editor.
“Calibration Blocks” on page
rx_datain (Receiver Input Data Pins)
Chapter 1: Transceiver Architecture in Stratix IV Devices
CM
CM
for the LVDS receiver input buffer
for the following receiver input
CM
settings of 0.82 V and 1.1 V
February 2011 Altera Corporation
Transceiver Block Architecture
1–201.