DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 801

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels When You Enable the Adaptive Equalization (AEQ) Feature
Combining Transceiver Channels When You Enable the Adaptive
Equalization (AEQ) Feature
February 2011 Altera Corporation
f
Create three Instances for steps 1, 2, and 3 with the following parameters:
Instance 1
■
■
Table 3–20. Instance 1 for Example 13
Instance 2
■
■
Table 3–21. Instance 2 for Example 13
Instance 3
■
■
Table 3–22. Instance 3 for Example 13
For more information, refer to
Alternate CMU PLL Option” on page
To enable the AEQ feature in a transceiver channel, select the Enable Adaptive
Equalization option in the Reconfig screen of the ALTGX MegaWizard Plug-In
Manager. When you select this option, the aeq_fromgxb and aeq_togxb ports are
enabled.
For more information about initiating the AEQ feature, refer to the “Adaptive
Equalization (AEQ)” section in the
chapter.
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 3
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 0
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 0
Main PLL
Main PLL
Main PLL
PLL1
PLL2
PLL3
PLL
PLL
PLL
“Combination Requirements When You Enable the Use
(Table
(Table
(Table
Dynamic Reconfiguration in Stratix IV Devices
SONET OC48
SONET OC48
3–42.
Data Rate
Data Rate
Data Rate
FC 2G
3–20)
OTU1
3–21)
3–22)
GIGE
GIGE
Stratix IV Device Handbook Volume 2: Transceivers
PLL Logical Reference Index
PLL Logical Reference Index
PLL Logical Reference Index
0
1
2
3
3
2
3–47