DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 51

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–12. LUT Register from Two Combinational Blocks
February 2011 Altera Corporation
datain(datac)
aclr
sclr
clk
Similar to the carry chains, the top and bottom halves of shared arithmetic chains in
alternate LAB columns can be bypassed. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in an LAB while leaving the other half
available for narrower fan-in functionality. Every other LAB column is top-half
by-passable, while the other LAB columns are bottom-half by-passable.
For more information about the shared arithmetic chain interconnect, refer to
Interconnects” on page
LUT-Register Mode
LUT-register mode allows third-register capability within an ALM. Two internal
feedback loops allow combinational ALUT1 to implement the master latch and
combinational ALUT0 to implement the slave latch needed for the third register. The
LUT register shares its clock, clock enable, and asynchronous clear sources with the
top dedicated register.
combinational blocks within the ALM.
Figure 2–12
2–18.
shows the register constructed using two
4-input
5-input
LUT
LUT
combout
combout
sumout
sumout
Stratix IV Device Handbook Volume 1
LUT regout
“ALM
2–15