DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 140

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–24
Figure 5–20. External Clock Outputs for Top and Bottom PLLs
Notes to
(1) You can feed these clock output pins using any one of the C[9..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. The CLKOUT1 and CLKOUT2 pins are
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Stratix IV Device Handbook Volume 1
dual-purpose I/O pins that you can use as two single-ended outputs or one differential external feedback input pin. The CLKOUT3 and CLKOUT4
pins are two single-ended output pins.
Figure
Top/Bottom
PLLs
5–20:
PLL_<#>_CLKOUT0p (1), (2)
clkena0 (3)
clkena1 (3)
m(fbout)
Figure 5–20
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
PLL_<#>_CLKOUT0n (1), (2)
shows the clock I/O pins associated with the top and bottom PLLs.
PLL_<#>_FBp/CLKOUT1 (1), (2)
clkena3 (3)
clkena2 (3)
PLL_<#>_FBn/CLKOUT2 (1), (2)
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
clkena4 (3)
clkena5 (3)
PLL_<#>_CLKOUT3
(1), (2)
February 2011 Altera Corporation
PLL_<#>_CLKOUT4
PLLs in Stratix IV Devices
(1), (2)
Internal Logic