DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 250

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

7–30
Figure 7–21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
Stratix IV Device Handbook Volume 1
Figure
DQS/CQ
DQS/CQ
Pin
Pin
7–21:
CQn
CQn
Pin
Pin
Figure 7–21
and CQn pins in the device where memory interfaces are supported on all sides of the
Stratix IV device.
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Δt
Δt
Δt
Δt
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Clock
DQS
IOE
IOE
DQS
Clock
IOE
IOE
DLL
to
DLL
to
to
to
shows how the DQS phase-shift circuitry is connected to the DQS/CQ
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
to IOE
CQn
Pin
Δt
“DLL” on page
DQS Logic
Blocks
to IOE
CQn
Pin
Δt
DQS/CQ
to IOE
7–31.
Pin
(Note
Δt
Chapter 7: External Memory Interfaces in Stratix IV Devices
DQS/CQ
to IOE
Pin
Δt
1),
to IOE
CQn
Pin
Δt
(2)
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Stratix IV External Memory Interface Features
Clock
Clock
DLL
DLL
DQS
DQS
IOE
IOE
IOE
IOE
to
to
to
to
February 2011 Altera Corporation
DQS Logic
Blocks
Δt
Δt
Δt
Δt
CQn
DQS/CQ
CQn
DQS/CQ
Pin
Pin
Pin
Pin