DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 529

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–69. Rate Match Insertion in Basic Single-Width Mode
Figure 1–70. Rate Match FIFO Full Condition in Basic Single-Width Mode
February 2011 Altera Corporation
rx_rmfifoinserted
rx_rmfifofull
dataout
datain
dataout
datain
D1
D1
K28.5
K28.5
Figure 1–69
skip patterns are required to be inserted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip
cluster has a /K28.5/ control pattern followed by one /K28.0/ skip pattern. The rate
match FIFO inserts only two /K28.0/ skip patterns into the first skip cluster to
maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/
skip pattern is inserted into the second cluster for a total of three skip patterns to meet
the insertion requirement.
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions.
The rate match FIFO in Basic single-width mode automatically deletes the data byte
that causes the FIFO to go full and asserts the rx_rmfifofull flag synchronous to the
subsequent data byte.
Figure 1–70
rate match FIFO becomes full after receiving data byte D4.
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that
causes the FIFO to go empty and asserts the rx_fifoempty flag synchronous to the
inserted /K30.7/ (9'h1FE).
First Skip Cluster
K28.0
D2
D2
K28.0
shows the rate match FIFO full condition in Basic single-width mode. The
shows an example of rate match FIFO insertion in the case where three
K28.0
K28.0
D3
D3
K28.0
K28.0
Three Skip Patterns Inserted
D4
D4
K28.5
K28.0
D6
D5
Second Skip Cluster
K28.0
K28.0
D6
D7
K28.0
K28.5
Stratix IV Device Handbook Volume 2: Transceivers
D8
D7
K28.0
Dx.y
D8
xx
K28.0
xx
K28.0
Dx.y
xx
1–85