DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 910

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–64
Figure 5–33. Write Transaction in Data Rate Division in Transmitter Mode
Note to
(1) For this example, you want to reconfigure the local divider settings of the transmitter channel to Divide by 4. Therefore, the value set at
Stratix IV Device Handbook Volume 2: Transceivers
rate_switch_ctrl[1:0] is 2'b10.
logical_channel_address
reconfig_mode_sel[2:0]
rate_switch_ctrl[1:0] (1)
Figure
5–33:
reconfig_clk
write_all
busy
For this example, the value set in the What is the number of channels controlled by
the reconfig controller? option of the ALTGX_RECONFIG MegaWizard Plug-In
Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. Also, you
must reconfigure the local divider settings of the transmitter channel whose logical
channel address is 2'b01.
transmitter mode.
3'bXXX
2'bXX
2'bXX
Figure 5–33
shows a write transaction in data rate division in
3'b011
2'b10
2'b01
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
2'bXX
2'bXX