DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 675
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 675 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Input Reference Clocking
Table 2–2. Input Reference Clock Source
February 2011 Altera Corporation
Notes to
(1) ATX PLLs do not have dedicated refclk pins.
(2) For more information, refer to
(3) For more information, refer to
(4) For better jitter performance, Altera strongly recommends using the refclk0 and refclk1 pins of the transceiver block located immediately
(5) Lowest number indicates best jitter performance.
Index
1
2
3
4
5
below the ATX PLL.
Table
Input Reference Clock Source
refclk0 and refclk1 pins of the same
transceiver block
refclk0 and refclk1 pins of other
transceiver blocks on the same side of
the device using the ITB clock lines
Clock output from the left and right PLLs
in the FPGA fabric with voltage
controlled oscillator (VCO) bypass mode
Clock output from the left and right PLLs
in the FPGA fabric
Dedicated CLK input pins on the FPGA
global clock network
(3)
2–2:
1
Receiver clock data recoveries (CDRs), CMU PLLs (when the CMU channel is
configured as a CMU) and ATX PLLs can derive the input reference clock from one of
the sources listed in
When a CMU channel is configured as a channel, its CMU PLL acts as a receiver CDR
and can derive the input reference clock sources 2 through 5 listed in the
You can also use the refclk pin of the other CMU channel within the transceiver
block as a clock source as long as the other CMU channel is not configured as a
Receiver only or Receiver and Transmitter channel. For example, the CMU0 PLL can
derive its input reference clock from the refclk1 pin if the CMU1 channel is not
configured as a Receiver only or Receiver and Transmitter channel.
When a CMU channel is configured as a channel, its refclk pin is used to receive
serial input data. As a result, the refclk pin is not available to provide the input
reference clock.
Table 2–3
Table 2–3. Input Reference Clock Frequencies for the 10G ATX PLL Clock
Clock Source
9.9 to 11.3
“Inter-Transceiver Block (ITB) Clock Lines” on page
“Configuration Examples” on page
Data Rate (Gbps)
lists the input reference clock frequencies allowed for the 10G ATX PLL.
(2)
Table
CMU PLL
2–2.
Yes
Yes
Yes
Yes
Yes
2–73.
Allowed Divider Values
6G ATX PLL
M = 16, N = 1
M = 16, N = 2
No
Yes
Yes
Yes
Yes
(1)
2–8.
10G ATX PLL
Stratix IV Device Handbook Volume 2: Transceivers
No
Yes
No
No
No
(1)
Reference Clock Frequency
CDR
Yes
Yes
Yes
Yes
Yes
562.5 to 706.25
281.25 to 322
(MHz)
Jitter Performance
Table
2
(5)
1
3
4
4
(4)
2–2.
2–3
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