DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 690

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–18
Stratix IV Device Handbook Volume 2: Transceivers
Figure 2–12
configured in Basic (PMA Direct) ×N mode running at 6.5 Gbps with a 20-bit FPGA
fabric-PMA interface width. Because all 24 channels on the right side of the device are
configured in Basic (PMA Direct) ×N mode, use the right PLL_R1 configured in VCO
bypass mode to provide the input reference clock to the 6G ATX PLL.
Because the data rate of 6.5 Gbps requires a left and right, left, or right PLL to meet
FPGA fabric-Transmitter PMA interface timing, the tx_clkout from one of the 24
channels is phase shifted using PLL_R2. Use the phase-shifted output clock from
PLL_R2 to clock the FPGA fabric logic that generates the transmitter parallel data and
control signals.
shows 24 channels on the right side of the EP4SGX530NF45 device
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
February 2011 Altera Corporation