DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 366

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

10–32
Table 10–7. PS Timing Parameters for Stratix IV Devices (Part 2 of 2)
Stratix IV Device Handbook Volume 1
t
t
t
t
Notes to
(1) This information is preliminary.
(2) This value is applicable if you do not delay the configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value is applicable if you do not delay the configuration by externally holding nSTATUS low.
(4) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
(5) Adding up t
F
CD2UM
CD2CU
CD2UMC
Symbol
Table
PS Configuration Using a Microprocessor
PS Configuration Using a Download Cable
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
10–7:
CH
f
1
and t
CL
equals to t
Device configuration options and how to create configuration files are described in
the
the Configuration Handbook.
In this PS configuration scheme, a microprocessor controls the transfer of
configuration data from a storage device, such as flash memory, to the target
Stratix IV device.
For more information about configuration and timing information, refer to
Configuration Using a MAX II Device as an External Host” on page
section is also applicable when using a microprocessor as an external host.
In this section, the generic term “download cable” includes the Altera USB-Blaster
universal serial bus (USB) port download cable, MasterBlaster serial/USB
communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV
parallel port download cable, and EthernetBlaster download cable.
In a PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the device using the USB Blaster, MasterBlaster,
ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.
After power-up, Stratix IV devices go through a POR. The POR delay depends on the
PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T
4 ms < T
all user I/O pins. After the device successfully exits POR, all user I/O pins continue to
be tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors, which are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
Device Configuration Options
CLK
POR
. When t
POR
Parameter
< 12 ms. During POR, the device resets, holds nSTATUS low, and tri-states
< 300 ms. When PORSEL is driven high, the fast POR time is
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
CH
is 3.2 ns (min), t
(4)
CL
must be 4.8 ns and vice versa.
and
Configuration File Formats
(Note 1)
t
4 × maximum
CD2CU
DCLK period
Minimum
period)
CLKUSR
—
55
+ (8532
Maximum
chapters in volume 2 of
150
40
—
—
April 2011 Altera Corporation
Passive Serial Configuration
10–25. This
“PS
Units
—
—
ns
s