DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 306

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

8–28
Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction
LVDS data rate = 1 Gbps; serialization factor = 10; input reference clock = 100 MHz
The following settings are used when generating the three output clocks using an ALTPLL megafunction.
The serial clock must be 1000 MHz and the parallel clock must be 100 MHz (serial clock divided by the
serialization factor):
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■
■
Stratix IV Device Handbook Volume 1
c0
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■
■
c1
■
■
■
c2
■
■
■
Frequency = 1000 MHz (multiplication factor = 10 and division factor = 1)
Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock
Duty cycle = 50%
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
Phase shift = (10 - 2) × 360/10 = 288° [(deserialization factor - 2)/deserialization factor] × 360°
Duty cycle = (100/10) = 10% (100 divided by the serialization factor)
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
Phase shift = (–180/10) = –18° (c0 phase shift divided by the serialization factor)
Duty cycle = 50%
Example 8–1
megafunction.
shows how to generate three output clocks using an ALTPLL
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
February 2011 Altera Corporation