DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 607

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–129. Rate Match Deletion in XAUI Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
dataout[3]
dataout[2]
dataout[1]
dataout[0]
datain[3]
datain[2]
datain[1]
datain[0]
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
Rate Match FIFO
In XAUI mode, the rate match FIFO is capable of compensating for up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The XAUI protocol requires the transmitter to send /R/ (/K28.0/)
code groups simultaneously on all four lanes (denoted as ||R|| column) during
inter-packet gaps, adhering to rules listed in the IEEE P802.3ae specification. The rate
match FIFO operation in XAUI mode is compliant to the IEEE P802.3ae specification.
The rate match operation begins after:
■
■
The rate match FIFO looks for the ||R|| column (simultaneous /R/ code group on
all four channels) and deletes or inserts ||R|| column to prevent the rate match FIFO
from overflowing or under-running. The rate match FIFO can insert or delete as many
||R|| columns as necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match
FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. If
an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the four
channels goes high for one clock cycle per deleted ||R|| column. If an ||R||
column is inserted, the rx_rmfifoinserted flag from each of the four channels goes
high for one clock cycle per inserted ||R|| column.
Figure 1–129
columns are required to be deleted.
For more information, refer to
The synchronization state machine in the word aligner of all four channels
indicates synchronization has been acquired by driving the rx_syncstatus signal
high
The deskew FIFO indicates alignment has been acquired by driving the
rx_channelaligned signal high
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
K28.3
shows an example of rate match deletion in the case where three ||R||
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
First ||R||
Column
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
“Rate Match FIFO in XAUI Mode” on page
K28.0
K28.0
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
Second ||R||
Column
Stratix IV Device Handbook Volume 2: Transceivers
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.0
K28.0
Third ||R||
Column
K28.0
K28.0
K28.0
K28.0
Fourth ||R||
Column
K28.0
K28.0
K28.0
K28.0
1–80.
K28.5
K28.5
K28.5
K28.5
1–163