DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 677

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Input Reference Clocking
Figure 2–3. Input Reference Clock Sources Across Transceiver Blocks
February 2011 Altera Corporation
To FPGA Fabric
Figure 2–3
receiver CDRs in four transceiver blocks on the right side of the EP4SGX530F45
device. In this figure, the input reference clock sources for four transceiver blocks are
located only on the right side of the device but the EP4SGX530NF45 device has similar
input reference clock resources available for the four transceiver blocks located on the
left side of the device as well.
Figure 2–3
of ITB clock lines available in any Stratix IV GX device is equal to the number of
refclk pins available in that device.
shows the input reference clock sources for CMU PLLs, ATX PLLs, and
also shows the ITB clock lines on the right side of the device. The number
ITB[7:0]
8
refclk0
refclk1
refclk0
refclk0
refclk0
refclk1
6
6
refclk1
6
refclk1
6
2
2
2
2
2
2
2
2
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
ITB Clock Lines
ITB Clock Lines
8
8
6
6
6
6
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL R1 (6G)
ATX PLL R0 (6G)
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
and
and
and
and
2–5