DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 792
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 792 of 1154
- Download datasheet (32Mb)
3–38
Stratix IV Device Handbook Volume 2: Transceivers
You can place these two instances in two transceiver blocks, as shown in
Figure 3–20. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct)
Configuration Using CMU PLL in Two Transceiver Blocks For Example 9
Note to
(1) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents
the ×N bottom clock line.
Figure
3–20:
CMU0
PLL
CMU0 Channel
Inst0:Channel 0
Inst0:Channel 1
Inst0:Channel 2
Inst0:Channel 3
Inst0:Channel 4
Inst0:Channel 5
Inst0:Channel 6
Inst0:Channel 7
Inst0:Channel 8
Inst1:Channel 0
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
Inst0:Channel 1
Inst0:Channel 1
(1.25 Gbps)
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
CMU PLL
GXBR0
GXBR1
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
Central
Divider
Clock
Combining Transceiver Channels in Basic (PMA Direct) Configurations
x1 Clock Line
x4 Clock Line (1)
xN Top Clock Line (1)
February 2011 Altera Corporation
Figure
3–20.
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