DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 639

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Auxiliary Transmit (ATX) PLL Block
Figure 1–159. PCIe Reverse Parallel Loopback Mode Datapath (Grayed-Out Blocks are Not Active in this Mode)
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation
Fabric
FPGA
6G ATX PLL Block
f
f
In
parallel loopback mode is enabled.
Stratix IV GX and GT transceivers contain the ATX PLL block that you can use to
generate high-speed clocks for the transmitter channels on the same side of the
device. Each:
■
■
For data rates supported by these ATX PLLs, refer to the
Devices
Stratix IV GX can have either two (one on each side of the device) or four (two on each
side of the device) 6G ATX PLLs, depending on the specific devices.
For data rates supported by 6G ATX PLLs, refer to the
Devices
Figure
Stratix IV GX device has 6G ATX PLL
Stratix IV GT device has 6G ATX PLL and 10G ATX PLLs
section.
section.
1–159, the grayed areas show the inactive paths when the PCIe reverse
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Byte Serializer
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B10B Encoder
Stratix IV Device Handbook Volume 2: Transceivers
Device Datasheet for Stratix IV
Reverse Parallel
Loopback Path
Device Datasheet for Stratix IV
Transmitter Channel
Receiver Channel
PMA
PMA
1–195