DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 466
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
1–22
Stratix IV Device Handbook Volume 2: Transceivers
The byte serializer forwards the LSByte first, followed by the MSByte. The input data
width to the byte serializer depends on the channel width option that you selected in
the ALTGX MegaWizard Plug-In Manager. For example, in single-width mode,
assuming a channel width of 20, the byte serializer sends out the least significant
word datain[9:0] of the parallel data from the FPGA fabric, followed by
datain[19:10].
in single-width mode.
Table 1–9. Input and Output Data Width of the Byte Serializer in Single-Width Mode
Figure 1–16
width, refer to
Figure 1–16. Byte Serializer Datapath in Double-Width Mode
Notes to
(1) For the datain[] and dataout[] port width, refer to
(2) The datain signal is the input from the FPGA fabric that has already passed through the TX phase compensation
The operation in double-width mode is similar to that of single-width mode. For
example, assuming a channel width of 40, the byte serializer forwards datain[19:0]
first, followed by datain[39:20].
the byte serializer in double-width mode.
Table 1–10. Input and Output Data Width of the Byte Serializer in Double-Width Mode
Asserting the tx_digitalreset signal resets the byte serializer block.
If you select the 8B/10B Encoder option in the ALTGX MegaWizard Plug-In Manager,
the 8B/10B encoder uses the output from the byte serializer. Otherwise, the byte
serializer output is forwarded to the serializer.
Single-width mode
Double-width mode
FIFO.
Double-Width Mode
Deserialization Width
Deserialization Width
Figure
shows the byte serializer datapath in double-width mode. For data port
1–16:
Table
Table 1–9
1–10.
lists the input and output data widths of the byte serializer
datain[]
Input Data Width to the Byte
Input Data Width to the Byte
Table 1–10
Byte Serializer
Serializer
Serializer
Chapter 1: Transceiver Architecture in Stratix IV Devices
32
40
/2
16
20
lists the input and output data widths of
Table
1–10.
Low-Speed Parallel
dataout[]
Clock
(Note
Output Data Width from the
1),
Output Data Width from the
February 2011 Altera Corporation
(2)
Transceiver Block Architecture
Byte Serializer
Byte Serializer
16
20
10
8
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