DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 994

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–36
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 2 of 3)
Stratix IV Device Handbook Volume 3
Create an rx_ctrldetect
port to indicate 8B/10B
decoder has detected a control
code.
Create an rx_errdetect port
to indicate 8B/10B decoder
has detected an error code.
Create an rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error.
Create an rx_runningdisp
port to indicate the current
running disparity of the 8B10B
decoded byte.
Flip receiver output data bits.
Flip transmitter input data bits.
ALTGX Setting
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric. This signal
indicates whether the decoded 8-bit code group is a
data or control code group on this port.
If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the
IEEE802.3 specification, this signal is driven high.
If the received 10-bit code group is a data code group
(/Dx.y/), this signal is driven low.
The signal width is 1, 2, and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric and indicates an
8B/10B code group violation.
This signal is asserted high if the received 10-bit code
group has a code violation or disparity error. It is used
along with the rx_disperr signal to differentiate
between a code violation error and/or a disparity error.
The signal width is 1, 2 and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric.
This signal is asserted high if the received 10-bit code
or data group has a disparity error. When this signal
goes high, rx_errdetect is also asserted high.
The signal width is 1, 2, and 4 bits for a channel width
of 8 bits, 16 bits, and 32 bits, respectively.
This is an output status signal that the 8B/10B
decoder forwards to the FPGA fabric to indicate the
current running disparity of the 8B/10B decoded byte.
This option reverses the bit order of the parallel
receiver data at a byte level at the output of the
receiver phase compensation FIFO. For example, if the
16-bit parallel receiver data at the output of the
receiver phase compensation FIFO is
'10111100 10101101' (16'hBCAD), enabling this
option reverses the data on rx_dataout port to
'00111101 10110101' (16'h3DB5).
This option reverses the bit order of the parallel
transmitter data at a byte level at the input of the
transmitter phase compensation FIFO. For example, if
the 16-bit parallel transmitter data at the tx_datain
port is '10111100 10101101' (16'hBCAD), enabling
this option reverses the input data to the transmitter
phase compensation FIFO to
'00111101 10110101' (16'h3DB5).
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Decoder” section in the
Transceiver Architecture in
Stratix IV Devices
“8B/10B Decoder” section of
Table 1-77 in the
Architecture in Stratix IV Devices
chapter.
February 2011 Altera Corporation
Reference
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Transceiver
chapter.
chapter.
chapter.
Protocol Settings