DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 274

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

7–54
Stratix IV Device Handbook Volume 1
Figure 7–34
Figure 7–34. Delay Chains in an I/O Block
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input.
DQS input path.
Figure 7–35. Delay Chains in the DQS Input Path
octdelaysetting2 (only)
octdelaysetting1 (only)
DQS
shows the delay chains in an I/O block.
rtena
D5 OCT
Delay
Chain
D6 OCT
Delay
Chain
DQS
Delay
Chain
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
D6 Output-
Enable Delay
Chain
D5 Output-
Enable Delay
Chain
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
oe
Figure 7–35
Chapter 7: External Memory Interfaces in Stratix IV Devices
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
D4 Delay
Chain
(outputdelaysetting2 +
outputfinedelaysetting2)
D6 Delay
Delay
Chain
D1 Delay
Delay Chain
shows the delay chains in the
Stratix IV External Memory Interface Features
(outputdelaysetting1 +
outputfinedelaysetting1)
dqsenable
dqsin
Enable
Control
Enable
D5 Delay
Delay
Chain
DQS
DQS
T11 Delay
Chain
February 2011 Altera Corporation
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dqsbusout