DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 527

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–66. Rate Match Deletion in GIGE Mode
Figure 1–67. Rate Match Insertion in GIGE Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
rx_rmfifodatainserted
dataout
datain
1
dataout
datain
The rate match FIFO can insert or delete as many /I2/ or /C2/ (first two bytes) as
necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted
for two clock cycles for each deleted and inserted /I2/ ordered set, respectively.
Figure 1–66
symbols are required to be deleted. Because the rate match FIFO can only delete /I2/
ordered set, it deletes two /I2/ ordered sets (four symbols deleted).
Figure 1–67
symbol is required to be inserted. Because the rate match FIFO can only insert a /I2/
ordered set, it inserts one /I2/ ordered set (two symbols inserted).
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions.
In GIGE mode, the rate match FIFO does not insert or delete code groups
automatically to overcome FIFO empty and full conditions, respectively. It asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively.
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Dx.y
Dx.y
Dx.y
Dx.y
shows an example of rate match FIFO deletion in the case where three
First /I2/ Ordered Set
shows an example of rate match FIFO insertion in the case where one
K28.5
K28.5
First /I2/ Ordered Set
K28.5
K28.5
D16.2
D16.2
D16.2
D16.2
/I2/ Ordered Set Deleted
Second /I2/ Ordered Set
Second /I2/ Ordered Set
K28.5
K28.5
Dx.y
K28.5
D16.2
D16.2
D16.2
Stratix IV Device Handbook Volume 2: Transceivers
K28.5
Third /I2/ Ordered Set
K28.5
D16.2
D16.2
Dx.y
Dx.y
1–83